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ADM1041
Bit No.
Name
R/W
Description
1–0
loadov_recover
R/W
b1
b0
Function
0
0
1
1
0
1
0
1
Add 100 μs delay
Add 200 μs delay
Add 300 μs delay
Add 400 μs delay
Table 13. Register 04h, Current Sense CC. Power-On Default from EEPROM Register 8104h during Power-Up.
Bit No.
7–3
2
1–0
Name
curr_limit
Share_OK_Window
Share_OK_thresh
R/W
R/W
R/W
Description
This register contains current sense trim level setting at which current limiting starts
Share_OK Window Comparator Thresholds
b1 b0 Function
0 0 ±100 mV
0 1 ±200 mV
1 0 ±300 mV
1 1 ±400 mV
Table 14. Register 05h, Current Share Offset. Power-On Default from EEPROM Register 8105h during Power-Up.
Bit No.
7–0
Name
I SHARE _offset
R/W
R/W
Description
This register contains current share offset trim level. Writing 00h corresponds to the min
offset. FFh corresponds to maximum offset. See the Current Limit Error Amplifier section in
the Specifications for more information.
Table 15. Register 06h , Current Share Slope. Power-On Default from EEPROM Register 8106h during Power-Up.
Bit No.
7–1
0
Name
ISHARE_slope
Reserved
R/W
R/W
X
Description
This register contains current share slope trim level.
Don’t Care
Table 16. Register 07h, EEPROM_lock . Power-On Default from EEPROM Register 8107h during Power-Up.
Bit No.
7
Name
Reserved
R/W
X
Description
Don’t Care
6
5
4
3
2
1
0
lock6
lock5
lock4
lock3
lock2
lock1
lock0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Locks 8140h–817Fh
Locks 8120h–813Fh
Locks 8100h–811Fh
Locks 80C0h–80FFh
Locks 8080h–80BFh
Locks 8040h–807Fh
Locks 8000h–803Fh
Available FRU.
ADI cal registers, Locked by manufacturer.
ADM1041 Config Boot registers.
Available FRU.
Available FRU.
Available FRU.
Available FRU.
Table 17. Register 08h, Load OV Trim. Power-On Default from EEPROM Register 8108h during Power-Up.
Bit No.
7–0
Name
load_ov
R/W
R/W
Description
Load OV trim
Table 18. Register 09h, Local UVP Trim. Power-On Default from EEPROM Register 8109h during Power-Up.
Bit No.
7–0
Name
local_uvp
R/W
R/W
Description
Local UVP trim
Rev. A | Page 43 of 64
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